module dequeuePortDeMuxer16 (
    input wire clk,
    input wire rst,
    input wire dequeue_vld_in,              //出栈使能
    input wire [5:0] dequeue_priority_in,
    input wire [15:0] dequeue_value_in,     //出队的内容
    output reg [15:0] dequeue_vld_out,
    output reg [5:0] dequeue_priority_out [0:15],
    output reg [9:0] dequeue_value_out [0:15]
);
    integer i;

    always @(posedge clk) begin
        if (rst) begin
            //复位信号拉高时，将所有的使能信号拉低
            dequeue_vld_out <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                dequeue_value_out[i] <= 0;
                dequeue_priority_out[i] <= 0;
            end
        end
        else begin
            if (dequeue_vld_in) begin
                if (dequeue_value_in[15:10] > 15) begin
                    dequeue_vld_out <= (1 << (dequeue_value_in[15:10]-16));
                    dequeue_priority_out[(dequeue_value_in[15:10]-16)] <= dequeue_priority_in;
                    dequeue_value_out[(dequeue_value_in[15:10]-16)] <= dequeue_value_in[9:0];
                end
                else begin
                    dequeue_vld_out <= 16'h0000;
                    for (i=0; i<16; i=i+1) begin
                        dequeue_value_out[i] <= 0;
                        dequeue_priority_out[i] <= 0;
                    end
                end
            end
            else begin
                dequeue_vld_out <= 16'h0000;
                for (i=0; i<16; i=i+1) begin
                    dequeue_value_out[i] <= 0;
                    dequeue_priority_out[i] <= 0;
                end
            end
        end
    end
    
endmodule